In recent years, with sophistication and diversification of functions of devices such as portable devices requiring reduced costs and low power consumption, these devices are required to have high processing speed. Manufacture and development of dedicated hardware are inevitable in order to obtain high processing speed compatible with low power consumption. However, with such functional sophistication and diversification, costs for manufacture and development of the dedicated hardware have increased every year.
For reduction of manufacture and development costs, semiconductor devices using a dynamically reconfigurable circuit technique have attained attention. An example of such semiconductor devices is disclosed in the following document, which will simply referred to as Sueyoshi:
Toshinori SUEYOSHI et al, “Reconfigurable System” Ohmsha, Ltd. Aug. 25, 2005, pp 189-208
The semiconductor device disclosed in Sueyoshi includes a two-dimensional array of processing elements (PEs) as basic elements for performing an operation process and a controller disposed in the middle of the PEs. Each of the PEs is an operating device which is capable of dynamically modifying a PE circuit configuration. Circuit information defining the kind of operation performed in each PE and a connection relationship between PEs is stored in an instruction memory contained in the semiconductor device. The PEs have their circuit configuration dynamically modified based on the circuit information stored in the instruction memory, exchange data therebetween, and perform the operation process.
It is preferable that such a semiconductor device has high processing performance even in low storage capacity of the instruction memory. However, the semiconductor device using a dynamically reconfigurable circuit technique as disclosed in Sueyoshi has a trade-off relationship between the storage capacity of the instruction memory and its processing performance.
For example, when the operation process performed in the PEs is changed and the circuit configuration of the PEs is dynamically modified, if the instruction memory has a storage capacity high sufficient to store any circuit information which is currently being used or used later, the PEs can perform the operation process based on the circuit information stored in the instruction memory without newly writing circuit information into the instruction memory. Then, the PEs may have higher processing performance since time taken to change the operation process becomes shorter.
On the other hand, if the instruction memory has a storage capacity so low as to store only the circuit information before change of the operation process performed in the PEs, it is necessary to write the circuit information after change of the operation process into the instruction memory. On this account, while the circuit information after the change is being written into the instruction memory, the PEs cannot perform the operation process, which results in deterioration of its processing performance.